1. Field of the Invention
This invention relates generally to MOS memory arrays and, more particularly, to MOS random access memory arrays that utilize memory cells having a single MOS device connected to a semiconductor capacitor device as the storage element of the MOS random access memory array.
2. Description of the Prior Art
In the past, memory cell designs for MOS random access memory arrays have developed from the use of multiple devices (four and three MOS device cells) to the present use of a single MOS device with a semiconductor capacitor to provide a single bit or memory element.
Due to the drive in the semiconductor memory industry to reduce costs, increase memory bit capacity and have high reliability and yields, the size and design of each memory cell and the MOS and semiconductor capacitor device thereof that would be used in a memory array become extremely important. Thus, it became critical to achieve optimum use of a single MOS memory device in combination with a semiconductor capacitor device for incorporation in advanced, MOS random access memory array designs. For example, although most semiconductor memory companies presently manufacturing MOS random access memory arrays in high volume with large amounts of memory per chip or die have implemented the use of a simple memory cell having a single MOS device and a semiconductor capacitor device combined to function as their memory bit element, the reduction of the memory cell size has become a critical factor in achieving the goals of reduced costs, increased memory bit capacity and chip yields. As a consequence, most of the 4K bit MOS random access memory arrays that are in production today as well as the 16K bit MOS random access memory arrays that are being developed and placed into manufacture presently incorporate a memory cell design which utilizes a single MOS device and connected semiconductor capacitor device for the memory element; however, reduction of the memory cell size is dependent on reducing the size of one or both of the devices of this memory cell. Thus, a need existed to reduce the size of one of the devices of the memory cell and thereby reduce the overall size of the memory cell.
In implementing the so called one (MOS) device memory cell design which utilizes a single MOS device in combination with a semiconductor capacitor, the general memory array design tendency was to have the MOS device connected to one plate of the semiconductor capacitor device and the other plate of the semiconductor capacitor device connected to a separate V.sub.DD line that was utilized in the reading and writing operation for the memory cells of the MOS memory array (a separate V.sub.DD line was generally used for each column (or row) of a line of memory cells). An example of this type of prior art MOS memory array design using a single MOS device and a capacitor as the memory element or bit of the array is shown in U.S. Pat. No. 3,940,747 (see FIG. 3). Thus, as can be seen with reference to FIG. 3 and FIG. 4 of this prior art patent, a separate V.sub.DD line was needed and used to connect up one plate of each of the capacitors of a line (row or column) of MOS memory elements. This type of MOS memory array design was very disadvantageous from an overall size and therefore cost viewpoint because of the fact that every line of MOS memory cells required a separate V.sub.DD line. This resulted in the loss of a great deal of semiconductor or silicon real estate due to the need to tie one capacitor plate to a V.sub.DD for every memory element in each row (or column) of the MOS memory array.
Accordingly, MOS memory cell and array designers sought another way of building MOS random access memory arrays using the single device cell concept and eliminating the many V.sub.DD lines. U.S. Pat. No. 3,838,404 was an implementation of a MOS memory array design which eliminated the use of separate V.sub.DD lines tied to one plate of the semiconductor capacitor device of each memory element. As can be seen with reference to FIG. 3 of this patent, a memory cell is shown which utilizes a single MOS device and a connected capacitor device with the plate of the capacitor device that is not connected to the MOS device being electrically connected to the next line of memory cell units. However, there is no disclosure, teaching, or suggestion in this prior art patent of how to best implement and utilize this type of memory array with a smaller memory cell design. More specifically, this prior art patent does not disclose, teach or suggest how to reduce memory cell size by the use of a semiconductor capacitor device that is optimumly designed to have a high capacitance value and use less silicon real estate than prior semiconductor capacitor structures or designs so that the total MOS random access memory array can be designed smaller and at the same time have very good performance.
Thus, there was a need to develop a MOS random access memory cell array which utilizes both an optimum layout design eliminating V.sub.DD lines and a smaller size MOS memory element that uses less semiconductor real estate.